The invention relates to a processor according to the preamble of claim 1 hereafter appended. At present, there is a trend in circuitry design towards building a so-called Digital Video Platform (DVP) that will perform various multimedia-processing functions. Such functions may be effected in hardware, in software, or in a mixture thereof, such choice depending on the processing function itself, and/or on the manufacturing volume of the function and/or circuit in question. The multimedia may include video, graphics, audio, or other.
For reasons of economy, quite often such processor will be dedicated to the execution of only a limited subset of those functions, often even to executing only a single one function. This policy will render a shared bus that connects the various processors to a background memory a key facility of an overall processing system. Now, for controlling the overall system, often furthermore a Central Processing Unit (CPU) will be provided. Next to controlling the background memory, the CPU may immediately access various control registers in the various processors. The number of such processors in realistic systems may have risen to 10-20.
The present invention is directed to solving a problem that has been recognized when designing a multi-function coprocessor that is able to perform both Motion Estimation (ME) and Motion Compensation (MC). These functions are used in video format conversion systems; some examples of such systems have been described by G. de Haan, et al., in an article “True motion estimation with 3-D recursive block batching”, IEEE Trans CSVT, October 1993, p. 368.388. In a complex system like this, the prevailing bandwidth on the shared bus is a prime design issue, and the various processors should maintain synchronization on the time slot level of the processing of an entire field or frame.